Nanosheet devices can be viable device options instead of fin field-effect transistors (FinFETs). For example, nanowires or nanosheets can be used as the fin structure in a dual-gate, tri-gate or gate-all-around (GAA) FET device. Complementary metal-oxide semiconductor (CMOS) scaling can be enabled by the use of stacked nanowires and nanosheets, which offer superior electrostatics and higher current density per footprint area than FinFETs. Additionally, nanosheet devices are being pursued as a viable device option for the 5 nm node and beyond. Nanosheet formation relies on the selective removal of one semiconductor (e.g., SiGe) with respect to another (e.g. Si) to form the nanosheet and GAA structures.
Work function metal (WFM) removal in nanosheet processing requires extensive over-etching to remove WFM layers in between nanosheets. Similar process requirements can exist for defining dual WFM, and multi-threshold voltage (Vt) devices.
Conventional lateral etch processes limit the minimum distance between n-type metal-oxide semiconductor (NMOS) and p-type metal-oxide semiconductor (PMOS) nanosheet devices, and limit the width of nanosheets. Due to increased device density being employed in many applications, reduced distance between n-type and p-type nanosheet devices is required. Accordingly, there is a need for improved WFM removal in nanosheet processing which allows for reduction of the distance between n-type and p-type nanosheet devices.